A byte-addressable computer has a small data cache capable of holding eight 32-bit words. Each cache block consists of one 32-bit word.
that means number of cache blocks = 8
cache size = 32 bytes, Block size = 4 bytes
Number of sets = total size / (block size * 2) = 32 / (4 *2) = 32 / 8 = 4
Here 4 way set associative is used, means number of blocks per set = 4 , and each block size = 4 B
| Tag bits |
set bits |
offset bits |
| 8 |
1 |
3 |
| address |
set |
Hit/miss |
| 200 |
0 |
compulsory miss |
| 204 |
0 |
compulsory miss |
| 208 |
1 |
compulsory miss |
| 20C |
1 |
compulsory miss |
| 2F4 |
0 |
compulsory miss |
| 2F0 |
0 |
compulsory miss |
| 200 |
0 |
Hit |
| 204 |
0 |
Hit |
| 218 |
1 |
compulsory miss |
| 21C |
1 |
compulsory miss |
| 24C |
1 |
compulsory miss |
| 2F4 |
0 |
Hit |
Total number of Hit = 3
out of 12 references 3 hits .
pattern is repeated 4 times..
for next iteration :
| address |
set |
Hit/miss |
| 200 |
0 |
Hit |
| 204 |
0 |
Hit |
| 208 |
1 |
Conflict miss |
| 20C |
1 |
Conflict miss |
| 2F4 |
0 |
Hit |
| 2F0 |
0 |
Hit |
| 200 |
0 |
Hit |
| 204 |
0 |
Hit |
| 218 |
1 |
Conflict miss |
| 21C |
1 |
Conflict miss |
| 24C |
1 |
Conflict miss |
| 2F4 |
0 |
Hit |
Total number of hit in 2nd iteration = 7
Now in 3rd iteration :
| address |
set |
Hit/miss |
| 200 |
0 |
Hit |
| 204 |
0 |
Hit |
| 208 |
1 |
Conflict miss |
| 20C |
1 |
Conflict miss |
| 2F4 |
0 |
Hit |
| 2F0 |
0 |
Hit |
| 200 |
0 |
Hit |
| 204 |
0 |
Hit |
| 218 |
1 |
Conflict miss |
| 21C |
1 |
Conflict miss |
| 24C |
1 |
Conflict miss |
| 2F4 |
0 |
Hit |
Total number of hit in 3rd iteration = 7
in 4th iteration , Total number of hit = 7 as this pattern is repeating..
so total hits = 3+7+7+7 = 24 out of 48 references .
hit rate = 24/48 = 0.5
so after 4 times repetition , hit rate = 0.5
