suppose that a computer has a processor with two L1 caches,one for instructions and one for data,and an L2 cache.Let t be the access time for the two L1 caches.The miss penalties are approximately 15t for transferring a block from L2 to L1,and 100t for transferring a block from the main memory to L2.For the purpose of this problem ,assume that the hit rates are same for instruction and data and the hit rates in the L1 and L2 caches are 0.96 and 0.80 respectively.
a)What fraction of accesses miss in both the L1 and L2 caches,thus requiring access to the main memory?
b)consider the following change to the memory hierarchy.The L2 cache is removed and the size of the L1 cache is increased so that their miss rate is cut in half.What is the average memory access time as seen by the processor in this case?
