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Suppose that in 1000 memory references there are 150 misses in first level and 100 miss in second level cache.
Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles.
If there are 4 memory references per instruction, the average stall per instruction is _________.

(ans given:78 )
asked in CO & Architecture by Active (1.1k points) | 75 views

1 Answer

+3 votes
150 miss in L1 all those will be searched in L2

so stall due to L1 miss = 150*50

100 miss in L2 all those will be searched in MM

so stall due to L2 miss =100*120

total stall = 150*50+100*120=19500

this is for 1000 memory reference

1 instruction = 4 memory reference

so 1000 memory reference = 1000/4 instruction = 250 instruction

so avg stall per instruction = 19500/250 =78 cycles
answered by Veteran (12.9k points)
Thank you. :)
miss rate in L1 per instruction will be (150/250) = (3/5)

miss rate in L2 per instruction will be (100/250) = (2/5)

(3/5)*(50) + (2/5) *(120) = 78 cycles here plzzz correct if  i am wrong


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