We know for direct mapping , CPU generated address is divided into :
a) Tag field b) Line field c) Word offset
Given , data memory size of cache = 16 KB
Assuming the memory to be byte addressable (i.e. 1 word size = 1 B) ,
No of cache lines = Data memory size of cache / Data size of 1 cache line
= 16 KB / 4 B
= 212 lines
So no of bits needed to represent cache line = log2 (212)
= 12 bits
No of bits needed to represent a word in a line = log24
= 2 bits
So no of bits needed for tag = 32 - 12 - 2
= 18 bits
Now for a given line , we will have the same tag ..
So 1 tag is associated with one line in case of direct mapping and associative mapping and with one set in case of set associative mapping..
So size of tag memory = No of tag bits * No of lines
= 18 * 212 bits
= 72 K bits
And size of data memory as mentioned earlier = 16 KB
= 128 K bits
So total memory needed for cache = 128 K bits + 72 K bits
= 200 K bits
