For the two-way cache:
Average memory access time2-way = Hit time + Miss rate × Miss penalty
= 1 + 0.049 × 10
=1.49
For the four-way cache, the clock time is 1.1 times longer.
The elapsed time of the miss penalty should be the same since it’s not affected by the processor clock rate, so assume it takes 9 of the longer clock cycles:
Average memory access time4-way = Hit time × 1.1 + Miss rate × Miss penalty
= 1x1.1 + 0.044 × 9 = 1.50
The number of cycles during which the processor is stalled waiting for a memory access, which we call the memory stall cycles. The performance is then the product of the clock cycle time and the sum of the processor cycles and the memory stall cycles
CPU execution time = (CPU clock cycles + Memory stall cycles) x Clock cycle time
This equation assumes that the CPU clock cycles include the time to handle a cache hit and that the processor is stalled during a cache miss.