Cache miss penalty

Question

Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L₂cache memory are 50 cycles. The hit time of L₂ cache is 10 cycles. The hit time of the L₁ cache is 5 cycles. If there are 1.25 memory references per instruction, then the average stall cycles per instruction is ________.

Can someone please tell me why don't we consider L1 hit time. Why can't the answer be 30/250(5 + (20/30)(10) + (10/30)(50+10)) ? 

Answer 1

memory stalls/m.m references = Miss in L1*Miss penaltyL1

MissPenalty L1 = HitTime L2 + MissInL2*MispenaltyL2

= 30/250*(10 + (10/30)*50)
= 3/25(10 + 50/3)
=3/25(80/3)=80/25=16/5

Avg stalls/ instructions = (no. of m.m stalls / m.m reference)*(mm ref/ins)
=16/5 * 1.25 = 4

Comments

it's given hit time of cache as 5 cycles, this time is not given to check whether it's a cache hit or miss.

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Just tell me one thing.

Hit time = time to read a word from the cache block after hit.

Or

Hit time = search time in cache + time to read a word from the cache block after hit.

I am not able to find the exact meaning anywhere.

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As we are talking here about miss penalty of L1 only when misses are there what would be stall cycles we are interested  in