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+9 votes

Consider the circuit shown below. In a certain steady state, the line $Y$ is at $'1'$. What are the possible values of $A, B$ and $C$ in this state?

  1. $A=0, B=0, C=1$

  2. $A=0, B=1, C=1$

  3. $A=1, B=0, C=1$

  4. $A=1, B=1, C=1$

asked in Digital Logic by Veteran (59.5k points)
edited by | 1.3k views
What is feedback on Y indicating...?Do we need to take into account...since it is a combinational circuit
Feedback on Y(Next state) is represented as y(present state) as input. and This is  asynchronous sequential logic circuit.
Answer could be either (B) or (D)  

Since what i got AssuMing as NOT gate

B'C=0    { B=0,C=0 OR  B=1,C=0 OR B=1,C=1}

A Could be anything bcoz we got 1+A'

3 Answers

+9 votes
Best answer
The figure is not clear- I assume there is a NOT gate just before taking Y making the final AND gate a NAND gate.

We have a steady state- meaning output is not changing. Y is 1 and remains 1 in the next state(s). So, we can write

$Y = \overline { \overline{(\overline{(AY)}. B )} . C} $

$ 1 = \overline {A} . B  + \overline{ C}$

So, $C = 0$ or  $\overline{A} . B = 1$

So, option B is TRUE.
answered by Veteran (353k points)
selected by
There is AND gate with C.

is that dot with Y considered as NOT.
I suppose that is what they meant- this figure being redrawn guess they made it like this :)
+2 votes
Y = ((AY)'B)'C = ((AY)'' + B')C = (AY + B')C
Y is 1 given.. then
C should be 1and either A is 1 or B is 0.
except B all are true.
answered by Veteran (54.9k points)
I don't think option A is correct.

As C should be 1 , the above circuit will become SR Latch with NAND Gate

Y = S'+ Ry    [Qn+1 = S'+ RQn] where S'R' should be 0 .
0 votes
the simplified expression is :-  ((AY')B)'C = Y'

therefore,C=1 ,Y=1 can be deduct from the problem .

now the more simplified expression becomes :-

((A'+Y)B)' = 0

or,((A'+Y)'+B') = 0

or, AY'+B' = 0

therefore B should be 0 to get a 1 in the last or operation as Y is 1.therefore options (a) & (C) are correct.
answered by (415 points)

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