3.6k views

A multi-user, multi-processing operating system cannot be implemented on hardware that does not support

2. DMA for disk transfer
3. At least two modes of CPU execution (privileged and non-privileged)
4. Demand paging
edited | 3.6k views
+3
Question now is corrected. the comment was before that :)
+1
can anyone please expail in detail. please i didnot get anything whatever was spoken above and bellow
0

@Arjun sir, I think address translation is not necessary for providing memory protection. We can also achieve this using "Relocation and Limit register mechanism".

"When the CPU scheduler selects a process for execution,the dispatcher loads the relocation and limit registers with the correct values as part of context switch.Because every address generated by the CPU is checked against these registers,we can protect both the operating system and the other user programs and data from being modified by the running process."

source:galvin chap-9

I think "only" for he purpose of memory protection if we use PT then it will be overhead while context-switch due to the large size of PT(while less overhead in limit and relocation register).

@Arjun sir, can you please check this.

+1
That mechanism is not efficient -- the memory space will have to be divided before hand among a "fixed" set of processes. So, this will limit the no. of processes to a small number.
0
yes sir I agree when It comes to efficiency then this method will not work.But we can't say that without address translation protection is not possible.

C) should be only correct option here.

Answer should be both (A) and (C) (Earlier GATE questions had multiple answers and marks were given only if all correct answers were selected).

Address translation is needed to provide memory protection so that a given process does not interfere with another. Otherwise we must fix the number of processors to some limit and divide the memory space among them -- which is not an "efficient" mechanism.

We also need at least $2$ modes of execution to ensure user processes share resources properly and OS maintains control. This is not required for a single user OS like early version of MS-DOS.

Demand paging and DMA enhances the performances- not a strict necessity.

Ref: Hardware protection section in Galvin

http://www.examrace.com/d/pdf/f54efd26/GATE-Computer-Science-1999.pdf

edited by
+1
Without the DMA the processor would have to do the IO by executing IO instrunctions, right ? So technically speaking a process will never get prempted as it will ALWAYS need the processor, there will be no waiting queue for IO, and not context switch ? Without context switching there will be no multi-processing ? So option B also will have to be part of the answer, right ?
+5
+1
+2
How does address translation provides the memory protection.?
+8
@rahul sharma

If more than one process is executing, then memory protection is required, because CPU may generate the same address and both the processes can wrongly read or write the data.
0
In multi processing and multi user os primary concern is security.this the reason to ensure security two modes are required.so ans should be A,Cbecouse both option deal with security.
+1

@Arjun sir,

How address translation is a necessity for providing memory protection.

Galvin says it can be provided only with the help of limit registers.

Since loading contents of limit registers is a privileged instruction, so we need two modes of execution for this.

+3
@Ayush, limit register is also the part of address translation.
+1

@reena_kandari .Cant we have just limit registers without address translation?Also,How exactly does address translation provides memory protection?Protection bits in page table or something else?

0
But in the absence of demand paging how will multiple processes co-exist in the main memory? There may be case that a process in particular is too big to fit in main memory or it alone occupies main memory completely and thus restricting other processes to get into main memory for processing (no multi processing).
+1

Limit : contains the range of logical addresses (i.e. size of the range)

Base and relocation reg: holds smallest legal physical address

There is another figure in Galvin which checks the logical address with the limit first and if the address is within the range (i.e. less than limit) then MMU maps the logical address dynamically by adding the value in the relocation register. So if the address generated by CPU is A then

in short : if A <Limit then Map(A+reloc).

In Ayush's figure, the logical address is first checked with the base. If address is more than equal to base then again it is checked with (base+limit).

Base <= A <Limit+Base

If the condition is satisfied then A has to be mapped to some physical address ( this is done by MMU).

So in both cases address translation is needed in the last step.

0

address translation requires for memory protection

https://gateoverflow.in/3366/gate2008-it-56

https://unix.stackexchange.com/questions/68148/what-information-exactly-is-in-the-access-control-bits-of-a-page-table

http://www.logix.cz/michal/doc/i386/chp05-02.htm

demand paging.

1
2
3
4
5
+1 vote
6