5,410 views

Suppose you want to build a memory with $4$ byte words and a capacity of $2^{21}$ bits. What is type of decoder required if the memory is built using $2K \times$ $8$ $\text{RAM}$ chips?

1. $\text{5 to 32}$
2. $\text{6 to 64}$
3. $\text{4 to 16}$
4. $\text{7 to 128}$

### Subscribe to GO Classes for GATE CSE 2022

here u have to built a memory using some chips so first of all wht u should now is the ram implementation. here it is

so the type of decoder required will dependent on the number of rows . not number of columns . columns are for data whenevr one row is selected the whole data on that row will be extracted by data lines . and that how each word size matters. if your memory is byte addressable then 8 vertical lines will be there if itis one word where each word is of two byte the  it will be 2*8= 16 as we know every row should accomodate one word if the memory is word addressable else one byte if byte addressable .

so leaving the chips required first of all take a look at what we have to make . given is 4 byte word memory . mens memory is word addressable where each word is of 4 byte . so data lines required will be 4*8=32 . and total capacity is 2^21 bit so number of rows required will be equal to 2^21/2^4=2^16

so here we are now with an idea of what e have to make

now finally we have to make it using 2k *8 chip which mens 2^11 rows . so now dividing 2^16/2^11 is the actual no of adress line required if i use these chips direct implementation will require 2^16 adress line .

so which is 32so we need a 5*32 decoder .

by
42 73 161

i don't know answer but options are:

a) 5 to 32          b) 6 to 64       c) 4 to 16            d) 7 to 128

but your explain seems to be correct. here RAM is 2K X 8  which means ram word size is 8 bits but our requirement is 32 bits.but you are saying data lines can vary, but in question it is given you have to make it using 2KX8 RAM,still can we increase data lines

for getting 32 u have to put sach 4 rams in series. i just make a diagram and show u .

now we have 32 address lines and 32 data lines .and made use of 2k*8 chips only .
and putting an warning that it may be wrong is just a precaution . seeing option i am sure it"s a according to me .u may upvote and choose it as a best answer. or cross check it . i think it 95% right.

you are 101% right.i have studied a lot about it and finally come up with the conclusion that you are right.

Memory interfacing is not in syllabus for GATE 2016.

http://syllabus.gatecse.in

Simple and understandable explanation.
Capacity of memory = 2^21 bit

So, Capacity of memory in Byte will be = 2^21/2^3 = 2^18 bytes

Word size of 4 Byte is given, from this we can calculate no. of words in memory = 2^18/ 2^2 = 2^16 words.

RAM chip size capacity is = 2K X 8 (means 8 bit word can be store in one cell of RAM), therefore, RAM capacity = 2^11 words.

No. of decoder line req. = 2^16/2^11 = 2^5 = 32
by

1
7,358 views