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Consider a two level cach system . For 100 memory references, 16 misses in the first level cach and 8 misss in the second level cache. Miss penalty from L2 cache to memory is 50 cycles. The hit time of L2 cach is 5 cycles and hit time of the L1 cache is 1 clock cycle. What is the average memory access time(in cycle)?
asked in CO & Architecture by Active (2.3k points) | 76 views

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hit ratio at level 1(H1)=(100-16)/100=.84

hit ratio at level 2(H2)=8/16= .5

miss penalty from L2=50 cycle

hit time in L1(T1)=1 cycle

hit time in L2(T2)=5 cycle

if hierarchical access happen then average memory time=

H1*T1+(1-H1)(T1+T2+H2*MISS PENALTY)

.84*1+.16(1+5+.5*50)=

5.8 CYCLE
answered by Active (1.7k points)
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Second line of your answer should be miss ratio. right?

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