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An instruction pipeline consists of 4 stages – Fetch (F), Decode field (D), Execute (E) and Result Write (W). The 5 instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below

No. of cycles needed for
Instruction F D E W
1 $1$ $2$ $1$ $1$
2 $1$ $2$ $2$ $1$
3 $2$ $1$ $3$ $2$
4 $1$ $3$ $2$ $1$
5 1 2 1 2

\begin{array}{|c|c|c|c|c|} \hline \textbf{Instruction} & \textbf {F} &\textbf {D} & \textbf {E} &  \textbf{W } \\\hline \textbf{1}& \text{$1$} & \text{$2$}  & \text{$1$} & \text{$1$} \\\hline \textbf{2} & \text{$1$} & \text{$2$} & \text{$2$}  & \text{$1$}\\\hline  \textbf{3}& \text{$2$} & \text{$1$}  & \text{$3$} & \text{$2$} \\\hline \textbf{4} & \text{$1$} & \text{$3$} & \text{$2$}  & \text{$1$} \\\hline \textbf{5} & \text{$1$} & \text{$2$} & \text{$1$}  & \text{$2$} \\\hline \end{array}

Find the number of clock cycles needed to perform the $5$ instructions.

edited | 1.6k views

$$\begin{array}{c|ccccccccccccc} &t_1&t_2&t_3&t_4&t_5&t_6&t_7&t_8&t_9&t_{10}&t_{11}&t_{12}&t_{13}&t_{14}&t_{15}\\\hline I_1&\text{F}&\text{D}&\text{D}&\text{E}&\text{W} \\ I_2&&\text{F}&-&\text{D}&\text{D}&\text{E}&\text{E}&\text{W}\\ I_3&&&&\text{F}&\text{F}&\text{D}&-&\text{E}&\text{E}&\text{E}&\text{W}&\text{W}\\ I_4&&&&&&\text{F}&-&\text{D}&\text{D}&\text{D}&\text{E}&\text{E}&\text{W}\\ I_5&&&&&&&&\text{F}&-&-&\text{D}&\text{D}&\text{E}&\text{W}&\text{W}\\ \end{array}$$

edited by
+10
I think this is the correct sequence of fetch , unless the previous instruction goes into the next stage (here it is D stage)the current instruction can not enter into F stage.
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@Arjun Sir then here we have assumed there is no data dependencies in instruction...I am just confused with the Execute of 1st instruction and decode of second instruction executing in the same column please clarify sir
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yes, no dependency is assumed..
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@Arjun sir, I have a doubt ,  I think F(fetch) operation of 2nd instruction should have started at 3rd clock cycle, otherwise it will overlap intermediate register's value and D(decode) operation of first instruction will not be executed correctly.

Similarly D(decode) operation of 3rd instruction should have started at 7th clock cycle, instead of 6th otherwise it will effect execution of 2nd instruction.

Please correct me if my understanding is wrong.

Thank you
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what will be the answer ...if FETCH of instruction 3 ..takes 3 cycle instead of 2 ? plz help  if you can..?
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Shreya Roy any references????

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@Bikram  @Arjun

why the fetch operation of 3rd instruction is not starting at 3rd clock cycle?

sameway why fetch of 5th instruction is not starting at 7th clock?
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thanks sir
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why the F(fetch) operation of 3rd instruction cannot start with 3rd cycle.....if it would then total 14 cycles will be there...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
F D D E W
F - D D E E W
F - D - E E E W W
F - D - - E E W
F - - - D - E W W

therefore 15 clock cycles needed.

+1
D of 3rd instruction is missing..
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oops ... I have edited the answer Please check it again ...
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please check IF(fetch) of I5. I think, it should be in clock 8 not in 7 as IF is not yet released by I4 .. And if we use the concept of the buffer then I2 and I3 should also use buffer concept  ??
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yes @vijaycs I5  should be in clock 8
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In 3rd instruction 1 F is missing
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This answer has changed the question
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
F D D E W
F - D D E E W
F F - D - E E E W W
F - D D D - E E W
F - - - D D - E W W

I think this should be correct answer

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​​​​​​instruction 3 -> clock 3

check again.

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@mehul vaidya, are you using concept of buffer? Because in question nothing is mentioned like that.

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@Shubhgupta we can't start decode 7th clock, 4th instruction untill 3rd instruction enters in new phase?

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@Shubhgupta

But from your comment can I conclude that

If there are two instruction Inst1 & Inst2 such that inst2 is next to inst1

then inst2 can not enter in particular state , until inst1 has done with that state in last cycle?