An instruction pipeline consists of 4 stages – Fetch (F), Decode field (D), Execute (E) and Result Write (W). The 5 instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below
Find the number of clock cycles needed to perform the $5$ instructions.
Answer is 15 cycles are required.
Shreya Roy any references????
therefore 15 clock cycles needed.
I think this should be correct answer
instruction 3 -> clock 3
@mehul vaidya, are you using concept of buffer? Because in question nothing is mentioned like that.
@Shubhgupta we can't start decode 7th clock, 4th instruction untill 3rd instruction enters in new phase?