An instruction pipeline consists of 4 stages – Fetch (F), Decode field (D), Execute (E) and Result Write (W). The 5 instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below
Find the number of clock cycles needed to perform the $5$ instructions.
Answer is 15 cycles are required.
Shreya Roy any references????
therefore 15 clock cycles needed.