Answer: 15 cycles are required.
Shreya Roy any references????
Fetch phase of instruction 3 can be started from 3rd cycle if inter stage buffers are assumed.. in this question answer will remain same (i.e. 15 clock cycles) in both cases.
But number of cycles will depend on whether pipeline buffers are used or not.
@Arjun sir , its necessary that if in any instruction stall occur , then in that particular cycle no instruction will execute . like in I4 , D could execute in t7. plz explain sir.
in T7, Decode phase of I4 can't happen.
why because, I3 doesn't moved to Execute phase, So I3 is in Decode phase. One phase can have atmost one instruction only.
if there is a stall, then in that clock, no further changes.
Ok so it means 1st comment of @shivam001 is correct.right ?
Regarding @Shreya Roy's comment, if you follow the pipelining lectures by Prof Matthew Jacob on NPTEL, he mentions that even if the previous instruction is undergoing a stall in that clock cycle, the hardware of that instruction's stage (for e.g., IF) is "occupied" and will be freed only when the instruction goes into the next stage.
So the current instruction is not allowed to do an IF stage in a cycle where the previous instruction is "stalled" in the IF stage.
(I take my words back) but see this answer--
@Verma Ashish Okay this is definitely confusing. On that answer I see an instruction running $S_1$ in a cycle where the previous instruction is stalled in the $S_1$ stage. What is the answer if we account for hardware being occupied like in this question?
therefore 15 clock cycles needed.
I think this should be correct answer
instruction 3 -> clock 3
@mehul vaidya, are you using concept of buffer? Because in question nothing is mentioned like that.
@Shubhgupta we can't start decode 7th clock, 4th instruction untill 3rd instruction enters in new phase?
Sorry For Too Late Reply.
But from your comment can I conclude that
If there are two instruction Inst1 & Inst2 such that inst2 is next to inst1
then inst2 can not enter in particular state , until inst1 has done with that state in last cycle?