@Arjun sir, I have a doubt , I think F(fetch) operation of 2nd instruction should have started at 3rd clock cycle, otherwise it will overlap intermediate register's value and D(decode) operation of first instruction will not be executed correctly.
Similarly D(decode) operation of 3rd instruction should have started at 7th clock cycle, instead of 6th otherwise it will effect execution of 2nd instruction.
Please correct me if my understanding is wrong.
Thank you