Q2 Q1 Q0 ( MSB - LSB)
There is a NAND GATE, if all 3 outputs are 1's then it will reset the counter as negative reset.
Our counter will go from 0 to 6, When o/p becomes 7 it will reset the counter, but...
frequency = 1GHZ, cycle time = 1/(1*10^9) = 1ns
Delay of NAND gate = 2ns, it means when output becomes 7, for the next 1 ns counter won't be reset and we can use the output.
I think answer should (D) mod 8 counter.