7,541 views
8 votes
8 votes

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero

If the clock (Clk) frequency is 1GHz, then the counter behaves as a

(A) mod-5 counter

(B) mod-6 counter

(C) mod-7 counter

(D) mod-8 counter

1 Answer

Best answer
7 votes
7 votes

Q2 Q1 Q0   ( MSB - LSB)

There is a NAND GATE, if all 3 outputs are 1's then it will reset the counter as negative reset.
Our counter will go from 0 to 6, When o/p becomes 7 it will reset the counter, but...

frequency = 1GHZ, cycle time = 1/(1*10^9) = 1ns
Delay of NAND gate = 2ns, it means when output becomes 7, for the next 1 ns counter won't be reset and we can use the output.

I think answer should (D) mod 8 counter.

selected by

Related questions

2 votes
2 votes
3 answers
2
Ravi_1511 asked Nov 18, 2016
1,169 views
Given the sequence 010202010 is generated from a sequential circuit of n flip-flops. And these flip-flops generate the sequence respectively. What is the minimum value of...
1 votes
1 votes
0 answers
3
2 votes
2 votes
0 answers
4
sh!va asked Dec 27, 2017
558 views
In this circuit, the race around(A) does not occur(B) occur when CLK = 0(C) occur when CLK =1 A= 1 and B =1(D) occur when CLK =1 A= 0 and B =0