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+35 votes

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Actually we need decoders for selection of a row from address lines not data lines.

So you have to concentrate upon the first term of each of RAM size and chip size which are 16 K and 1 K respectively.

So no of address lines = 16K / 1K

= 16

Hence we can use 4 : 16 decoder for this .But we have to realise this using 2 : 4 decoder.

So this question now becomes actually of realisation of 4 : 16 decoder using 2 : 4 decoders.

So 4 decoders are required in inner level as from 1 2:4 decoder we have only 4 output lines whereas we need 16 output lines.

Now to point to these 4 decoders , another 2 : 4 decoder is required in the outer level .

Hence no of 2 : 4 decoders to realise the above implementation of RAM = 1 + 4

= 5

Hence B) is the correct answer.

So you have to concentrate upon the first term of each of RAM size and chip size which are 16 K and 1 K respectively.

So no of address lines = 16K / 1K

= 16

Hence we can use 4 : 16 decoder for this .But we have to realise this using 2 : 4 decoder.

So this question now becomes actually of realisation of 4 : 16 decoder using 2 : 4 decoders.

So 4 decoders are required in inner level as from 1 2:4 decoder we have only 4 output lines whereas we need 16 output lines.

Now to point to these 4 decoders , another 2 : 4 decoder is required in the outer level .

Hence no of 2 : 4 decoders to realise the above implementation of RAM = 1 + 4

= 5

Hence B) is the correct answer.

+25 votes

Number of chips required =(16K*16)/(1K*8)=16*2 (i.e 16 chips vertically with each having 2 chips horizontally. So to select one chip out of 16 vertical chips, we need 4 x 16 decoder. Available decoder is – 2 x 4 decoder, to be constructed is 4 x 16 decoder

So 16/4=4, 4/4=1 Hence 4+1=5 decoders.

So 16/4=4, 4/4=1 Hence 4+1=5 decoders.

+23 votes

No. of 1K x 8 chips required = $\frac{16K * 16}{1K * 8}$

= ** 16 * 2 **chips (

Now, in order to access this bigger memory we need to choose one of the 16 rows.

Let us see how many address lines are required :

Total memory = 16K * 16

= 16K words ($\because$ 1 word = 16 bits here)

= $2^{14}$

Hence ** 14** address lines are needed to access the memory. Let the address be represented by

We can observe that we need *10 address bits *to access each of the *1K * 8 Chip *

Remaining Address bits = 14 - 10

= **4 Address bits**

Let us suppose we use the least 10 bits to address 1K*8 chip (Since it has 1024 words, we need 10 bits).

We can implement the decoders using the Higher 4 bits as shown in the picture (Picture is self Explanatory)

0

Remaining Address bits = 14 - 10 = **4 Address bits**

**what should b do that means of reamining address bits?**

+12 votes

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