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A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is

(A) 4      (B) 5      (C) 6      (D) 7
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which topic ?

Actually we need decoders for selection of a row from address lines not data lines.

So you have to concentrate upon the first term of each of RAM size and chip size which are 16 K and 1 K respectively.

So no of address lines  =  16K / 1K

=   16

Hence we can use 4 : 16 decoder for this .But we have to realise this using 2 : 4 decoder.

So this question now becomes actually of realisation of 4 : 16 decoder using 2 : 4 decoders.

So 4 decoders are required in inner level as from 1 2:4 decoder we have only 4 output lines whereas we need 16 output lines.

Now to point to these 4 decoders , another 2 : 4 decoder is required in the outer level .

Hence no of 2 : 4 decoders to realise the above implementation of RAM  = 1 + 4

=  5

Hence B) is the correct answer.
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got it. thanks @habibkhan
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@Arjun Sir,@Habib Sir:-

16K*16 Ram requires 14 bits to access 16K location.

But with the decoder we will be addressing 16 lines with 4 bits.

But in that particular chip we have 1K locations,so we need that 10 bits to select a particular cell in chip.Who that will be handled?
Number of chips required =(16K*16)/(1K*8)=16*2 (i.e 16 chips vertically with each having 2 chips horizontally. So to select one chip out of 16 vertical chips, we need 4 x 16 decoder. Available decoder is – 2 x 4 decoder, to be constructed is 4 x 16 decoder
So 16/4=4, 4/4=1 Hence 4+1=5 decoders.
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@habibkhan @arjun sir,

wont we be requiring more decoders for word size expansion from 8 bits to 16 bits ?
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Plz check my explanation @ravi_ssJ4

No. of 1K x 8 chips required = $\frac{16K * 16}{1K * 8}$

= 16 * 2 chips ( Each row has two 1K*8 chips and a total of 16 rows)

Now, in order to access this bigger memory we need to choose one of the 16 rows.

Let us see how many address lines are required :

Total memory = 16K * 16

= 16K words ($\because$ 1 word = 16 bits here)

= $2^{14}$

Hence 14 address lines are needed to access the memory. Let the address be represented by A13A12...A1A0

We can observe that we need 10 address bits to access each of the 1K * 8 Chip

Remaining Address bits = 14 - 10

Let us suppose we use the least 10 bits to address 1K*8 chip (Since it has 1024 words, we need 10 bits).

We can implement the decoders using the Higher 4 bits as shown in the picture (Picture is self Explanatory)

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what should b do that means of reamining address bits?

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We need A13A12...A1A bits to address the complete 16K*16 RAM.

We use  A- Aaddress each 1K*8 RAM chip, when it gets selected.

We have to A13 - A10  for use of control purpose, i.e., for use of decoders, selection one among 16 rows etc.

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Why to use 4:16 i am taking about input 4?
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@Uzumaki Naruto,For 1K*8,wouldn't the address bits be 13 instead of 10?Please correct me if I am wrong here. :)

Hence, a total of 5 Decoders are required.

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Can you explain in more detail?
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element left side to ) denote no. of rows. and element right to ( denote no. of column.for a table structure. since 16 rows and 2 column total 32 rams are required. so log 32 with base 2= 5 decoder
(B).

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