Here is a simple problem from Stallings.My confusion is with the offset bits in the address.If we are not mentioned anything about word addressing and byte addressing,what is the safest thing to assume? For example below exercise from Stallings.
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associa-
tive cache. Assume that the cache has a line size of four 32-bit words. Draw a block di-
agram of this cache showing its organization and how the different address fields are
used to determine a cache hit/miss. Where in the cache is the word from memory lo-
cation ABCDE8F8 mapped?
Now the format of the address is,
Offset-4 bits,Set-8 bits,Tag-20 bits.
Now is this offset - word or byte offset??...As per the question it looks like we need to address 4 words in a line that make 2 bits in LSB for a word offset,but then why 4 bits are used for?Even if it is used last two bits (LSB) will be always 00.The offset can be one of the following only
0000,0100,1000,1100.
Is it because we want to support byte level addressing as well?Or is it that we cannot support Word level addressing without using byte level addressing internally?Hence it is like 2 bits for word addressing and 2 bits for internally selecting byte inside a word??