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@stblue 

I think there is nothing like only adjacent instructions will have RAW dependency.

Because if Inst i writes r0, and this r0 is read by i+1, then it creates RAW hazard because Inst(i+1) reads before inst(i) writes it, and other subsequent inst (i+2) also needs to read data item r0, then it will also doing the same thing as like inst i+1, i.e. it is reading old value of r0 not MODIFIED VALUE.

And this will continue till Inst i completely writes the r0 into the register file, 

When Inst i successfully writes the data item i, and then other inst after inst i say inst j read the modified value of r0 written by inst i, which is actually we want,

REF:- https://courses.cs.washington.edu/courses/cse378/09au/lectures/cse378au09-15.pdf

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@stblue

firstly there is diffrence between hazard and dependency, not all dependecy is hazard, hazard comes to action only if stalls the pipeline..there are several cases where there can be RAW dependency but it will not lead to hazard.
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@joshi_nitish 

in this also we have dependency between sub and sw instruction but it will not create hazard in the pipeline because of this dependency.

ryt??

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yes, there will be no hazard.
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@joshi_nitish @shubhanshu thanks for clearing certain things out, I do believe adjacency and non adjacency need not matter while looking for dependency. Also it will depend on when result of Execution stage is going to available, if execution stage takes more number of cycle, then definitely non adjacent instruction will suffer because of dependency.
Taking reference of this question https://gateoverflow.in/3622/gate2006-it-78
Its previous year gate question, here if we consider only adjacent instruction, then no option matches, definitely we need to look for  non adjacent instructions as well.

Next to check for hazard, we need to draw pipeline diagram. If stalls are present then only that dependency will lead to hazard.

Correct me if iam still making any mistake. 

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