gate overflow

Question

Consider a 2 - way set associative cache memory with 4 sets and total
8 cache blocks (0 - 7) .Main memory has 64 blocks (0 - 63). If LRU
policy is used for replacement and cache is initially empty then total
number of conflict cache misses for the following sequence of
memory block references is :
0 5 9 13 7 0 15 25
A. 2
B. 3
C. 0
D. 1

Is ans is B?

Comments

Conflict are for 13 and 25.

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two conflict misses are for memory block addresses 13 and 25...

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Given ans is 0 is it true .

conflict miss is 2

 

5 ->13

and 9->25

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i am also getting 2 at 13 and 25