What is the maximum speedup achieved in new pipeline system?

Question

Consider a pipeline with 5 stages and each stage with delay as shown below :  IF  ID  EX  MEM  WB 400 ps  225 ps  350 ps  450 ps  300 ps    Try to improve performance above pipeline, you have decided to break up 2 of the above stages into 2 shorter stages.we have Number of instruction equal to 2. What is the maximum speedup achieved in new pipeline system?

Edit Similar gate question :https://gateoverflow.in/118719/gate2017-1-50

Comments

450/350=1.2857

---

@sachin! is correct.

---

Can you please explain in detail and answer given is 0.964.

---

How exactly is the speedup calculated? Do we just consider the cycle time of both old and new pipelines or execution time? If we take the former alone we get 1.28 and 0.91 from the latter.

I think we should consider execution time i.e 

(5 * 450)/(7*350)  = 0.91  

5 being the number of cycles of old pipeline and 7 for the new.

Answer 1

Number of instructions = 2
Number of clock cycles=k+(n-1)clocks
k:number of stages
n:number of instructions
Number of cycles = 7 + (2 – 1) clocks
= 8 clocks

Cycle Time = Maximum stage delay + Register delay
Since nothing is mentioned about register delay we consider it as 0.
Cycle Time = 350ps

CT_new = 8 * 350 ps
= 2800 ps 

for old pipeline

Number of cycles = 5 + (2 – 1) clocks
= 6 clocks

CT(old)=6*450=2700 ps

Speedup = CT_old / CT_new = 2700 / 2800 = 0.964

Comments

Try to improve performance above pipeline, you have decided to break up 2 of the above stages into 2 shorter stages

which two stages you made 350 ? why not make them 300 ? That'll improve the performance even more right?
@sunil how you got 350 for new pipeline, im not getting, could you please let me know ?

---

I think this way even answer was in terms of formula

we take max out of each stage delay so 450 for first pipeline

now additional delay 450*1 instruction*(5)first instruction will go to all five stages  
after that each instruction will complete in one cycle

so 450*1*5+ 450*1*1(this is remaining one instruction)

2700

now we have to break two stages in two smaller

400 --> 200 200
450 --> 225 225

now for this new pipe line we have max stage delay 350

now additional delay 350*1 instruction*(7)first instruction will go to all seven stages

so 350*1*7+ 350*1*1(this is remaining one instruction)

2800

---

Oh okay thanks, I misunderstood the question, got it now

Answer 2

When both pipelines become stable, then for each cycle both pipeline processors will process 1-1 instruction.

clock cycle time for processor 1 will be 450ps and for processor 2 clock cycle time will be 350ps.

speedup =450/350 = 1.2857

Comments

number of instructions is 2 here, your formula is valid only when (k + n - 1) $\approx$ n i.e. for large number of instructions

---

its not his mistake ,actually i did edit afterwards.

can you please answer this https://gateoverflow.in/155794/calculate-sum-of-war-raw-and-waw-dependencies-instructions and https://gateoverflow.in/155785/how-structural-hazard-is-possible-for-following