A 5-stage pipeline has a Register File that can execute either a Read operation (of 1 or 2 registers) or a Write operation (into only one register), but not both, during every clock cycle. The instruction mix that the processor executes contains 47% ALU instructions,24% Load, 11% Store and 18% Branch. Ignoring any data hazards and control hazards that may occur, what is the speedup of the pipeline that has a Register File capable of performing two reads and one write every cycle over the pipeline with the limited Register file?
