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The only instruction in the 5-stage pipelined MIPS that needs all 5 stages is Load. It has been suggested to design a 4-stage pipeline where the 4th stage will allow either a memory (read or write) operation, or a Register File write. The Load instruction will then be replaced by two instructions: Load-A (read from memory) and Load-B (write into the register file). The instruction mix that the processor executes contains 46% ALU instructions, 22% Load, 12% Store and 20% Branch. Ignoring all hazards and assuming that the two pipelines will have the same cycle time, what is the speedup of the 5-stage pipeline over the 4-stage one?
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lets assume 100 instruction out of which 78 are ALU and other instruction and 22 are load instruction 

for 5 stage pipeline 

number of cycle required 5 + 99 => 104

and time taken = 104n (lets assume each stage takes n seconds)

for 4 stage pipeline 

the load instruction will divide into 2 instruction therefor 22 instruction become 44 instruction  hence 

total instruction = 78 (ALU and other instruction) + 44 (load instruction )

number of cycle required = 4 + 121 => 125

and time taken = 125n

speed up = 125n/104n => 1.2

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