SPEEDUP CPI

Question

.  A program running on a non-pipelined processor executes 15% load instructions (5 cycles),
 20% store instructions (4 cycles), 15% branch instructions (3 cycles) and 50% ALU instructions
 (4 cycles). What is the CPI?  

Now we execute this program on a 5-stage pipelined processor with a single-port memory that can
 do either an instruction read or a data read (or write) in one cycle, ignoring data and control
 hazards (only consider structural hazards). What is the speedup over the previous one?

Comments

is it 2.963 ?

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you are right thank u

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@G.K.T Can you please explain the second part?

Answer 1

CPI for non pipelined processor :

occurrence of certain type of instruction  x cycles taken by that instruction

(0.15 * 5) + (0.2 * 4) + (0.15*3) +
(0.5 *4) = 4.00

Speedup if this is executed on a 5 stage pipelined processor :

speedup = CPI ( non pipelined) / CPI ( pipelined)

In an ideal pipeline CPI =1

but as mentioned in question it will either fetch instruction or store/load in a cycle

so loading( data read) and storing ( data write) will take additional cycles

1 ( what an ideal inst take in pipeline) + ( load or store *1)

1+ (0.15+0.2)*1

1.35

speedup 4.00/1.35 = 2.963

Comments

ok, so for pipeline CPI , we need to calculate Load-Store memory operation separately. right?