2 votes 2 votes Suppose there is unpipelined processor with cycle time 30 ns,which is evenly divided into 5 pipeline stages. The total latch latency of the pipeline will be____________ns CO and Architecture co-and-architecture pipelining + – srestha asked Oct 9, 2017 retagged Nov 13, 2017 by Arjun srestha 258 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.