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A 4 staged pipelined processor  IF = 2clocks /word and ID = 2clocks / word, Execute stage takes 2 clocks for register operands and 3 clocks for memory operand , WR takes 2 clock cycles

instruction size in words
MOV R1 (R2+300) 3
ADD R1 ,R2 1
MOV (R1 +400) ,R2 3
MOV(R2 +500),R1 3

Min number of clocks neede to complete

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