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Given that L1 instruction and L1 data cache are connected to CPU directly,

(doubt: does it mean they're independent?)

Each instruction fetch means a reference to the instruction cache and 35% of all instructions reference data memory. The average miss rate in the L1 instruction cache was 6%.The average miss rate in the L1 data cache was 14%.In both cases, the miss penalty is 12 clock cycles. What is overall miss penalty in clock cycles?

Doubt: Now it is given that 35% of all instructions reference data memory, so should we consider 65% of all instructions reference instruction memory or not ?

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Here we have to understand the two types of architectures : 

a) Von Neumann architecture : Here both the data and the instruction are in the same memory , so is the case with cache memory.

b) Harvard architecture : Here we use separate memories to store instruction and data.

So accordingly we access memory during instruction fetch and if needed during operand fetch or write in case it is a LOAD/STORE instruction.

So stall due to instruction fetch   =   Miss rate in L1 instruction cache * Miss penalty

                                                =   0.06 * 12

                                                =   0.72

Stall due to data fetch                =   Fraction of data fetch based ins(like LOAD etc) * Miss rate in L1 data cache * Miss penalty

                                                =   0.35 * 0.14 * 12

                                                =   0.588

Hence overall miss penalty      =    0.72 + 0.588

                                                =    1.308

Here the key point as mentioned above also that instruction cache and data cache are separate here and hence independent of each other.Hence instruction fetch miss includes all types of instructions regardless of type of instruction but for data cache miss it only holds if the instruction is operand fetch/write based instruction.

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