Memory Interfacing problem in Computer Organisation and Architecture

Question

Hi All,

I have one doubt regarding avg access time in various levels of memory. There are 2 ways in which the processor is connected to various levels of memory.

2 levels

Case 1:

(parallel access)

T avg = H1 * T1 + (1- H1) * T2;

Case 2:

(sequential access)

T avg = H1 * T1 + (1- H1) * (T1+T2);

In maximum Gate previous years problem, they are using case 1 only.

Consider this Gate 2004 problem,: You solved this via case 1.

Problem:

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Consider a system with 2 level cache. The access time of L1, L2 cache and memory are 1ns,10ns,500 ns. Hit rates of L1 and and L2 cache are 0.8 and 0.9, What is the avg access time of the system ignoring the search time within the cache?

===> Ans is 12.6, nothing is mentioned solved via case 1 only.

Can anyone please let me know which one should I use. Thank you.

Comments

0.8*1+0.2*0.9+0.2*0.1*500=12.6.
got any idea what I am doing?

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My question is which formula to use and when. I know here this one is used but sometimes are solved using hierarchical method i.e case 2.

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@souravsaha, in the question if it is given, The Deciding Sentence:-

When there is a miss in ith level the block is transferred from (i+1)th level to ith level.

then we use hierarchal access.

And, if nothing is mentioned then use your case 1.

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@ Shubhanshu  So does it means that hierarchical access is explicilty stated like the one you mentioned otherwise it's simultaneous Could you post some thread on go for this?

Answer 1

Here level wise memory access will be done that is case 2, because:-

In the question if you would have noticed that they have given  "ignoring search time with in the cache" means you have to access memory level wise.

'L1' memory be the cache w.r.t 'L2' similarly 'L2' will be cache w.r.t 'Main memory'.

Tavg=  H1*T1 + (1-H1)(H2)(T2+0) + (1-H1)(1-H2)(T3+0+0).

Tavg= 0.8*(1ns) + 0.2*0.9*(10ns) + 0.2*0.1*(500ns) = 12.6ns

Hope this makes clear.