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in Digital Logic by (141 points) | 387 views

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Clock pulse ↓   state (q2q1q0)↓

Starting                     000

1st clock                   001

2nd clock                 010

3rd clock                  100

4th clock                   011

5th clock                   111

6th clock                   100

7th clock                   010

8th clock                   100

9th clock                   010
by Veteran (60.5k points)
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Hi laser , Pranay Datta 1,Pooja Palod

Can you please explain how u r getting  001 in second cycle ? 

Also , I am not getting the data feed . 100 110 000 -- should I take from the right most side or left most side ?

0
Start feeding input from right side ie MSB
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Ans is C

010
by Boss (10.4k points)
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