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+4 votes

GATE -2009 

A CPU generally handles an interrupt by executing an interrupt service routine

  1. As soon as an interrupt is raised.

  2. By checking the interrupt register at the end of fetch cycle.

  3. By checking the interrupt register after finishing the execution of the current instruction.

  4. By checking the interrupt register at fixed time intervals

I am having confusion between option A and C...

For hardware interrupt option A is suitable and for software interrupt option C

in CO and Architecture by
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i think bro it says preempt process doesn't say that instruction is left as it is and  we served the INTERRUPT...
can't find a suitable answer ...bro
i order to execute the instruction we store our temporary results in i am executing 1st inst....say interrupt i will let complete the conctent of register in memory...and then will allow the ISR to take control...
still i think we should wait for someone to give most approprite answer....

3 Answers

+2 votes

Whenever a CPU is trying to execute an instruction, it is going to fetch the instruction, decode it, perform the operations and then write back the result. This entire thing is called as Instruction execution and this instruction execution is a kind of Atomic operation. Now, after one instruction is executed, CPU check the Interrupt Flag. If Interrupt Flag = 1, it will get into a Hardware Cycle, which will take control of CPU (i.e. no User process is executed during this time) and perform some certain actions. Since, we are moving from a User mode to Superior mode (OS/Kernel mode), we need to Store the Context of the processor (The CPU hardware thread only runs one program at a time, and it can context switch between multiple programs dozens, hundreds, or even thousands of times per second) such as Address of the Instruction where we have left, Program Status Word, Program Registers, etc. This information might change during the Interrupt Service Subroutine (which is executed in response to an interrupt). 

Therefore, we just cant simply call ISR, as soon as, an interrupt is detected. 

Hope, you are able to understand this.

+1 vote
answer should be 3 that is CPU always check the interrupt after the execution of current instruction...not in between phases...


       if we allow CPU to handle interrupt in between phases like fetch ,decode....THE INTERRUPT SERVICE ROUTINE may changes the values of registers its very we are loosing register contents...

hence CPU look out for interrupt after execution of current one....

one more point .....we can allow DMA in between any phase because DMA will simply grab bus will not change content of registers..
my doubt is different

As we know H/W interrupt is serviced as soon as the interrupt occurs

bt S/W interrupt waits a while for the CPU to complete its current execution  and then processes the interrupt
0 votes
Assume that an interrupt request arrives during execution of instruction i. The processor first completes execution of instruction i. Then, it loads the program counter with the address of the first instruction of the interrupt-service routine. After execution of the interrupt-service routine, the processor returns to instruction i + 1. Therefore, when an interrupt occurs, the current contents of the PC, which point to instruction i + 1, must be put in temporary storage in a known location. A Return-from-interrupt instruction at the end of the interrupt-service routine reloads the PC from that temporary storage location, causing execution to resume at instruction i + 1.

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