edited by
8,546 views
12 votes
12 votes

Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for additional circuitry like buffering and decoding.

  1. $0$          
  2. $1$            
  3. $2$            
  4. $3$
edited by

5 Answers

Best answer
23 votes
23 votes

Answer: (d)

Explanation:

  • A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.
  • CPU frequency is 33 MHz means 1 clock time is 1 / (33*106) = .03030 X 10-6 sec = 30.30 ns
  • Memory access time is 60 ns + 10ns = 70 ns
  • No. of clocks need to access memory = 70 ns / 30.30 ns = $\left \lceil 2.31 \right \rceil$ = 3
  • Implies that in 3rd clock operation will complete. So no. of wait states 3.

Reference: https://en.wikipedia.org/wiki/Wait_state

edited by
10 votes
10 votes
we need to find the number of WAIT STATES... i.e. the amount of time we have to make CPU wait such that memory is ready with the data that CPU would need, by that time. means -- at the time CPU needs data from memory the data should be present (after having sent from memory and crossed the intermediate circuitry) SINCE, CPU is faster and MEMORY Is slower so we have to make CPU wait(i.e. ADD WAIT STATES) Here, 33MHz CPU means cycle time of CPU is 30.30 ns( since 33MHz= 1/(33*10^6) seconds =30.30 ns) thus CPU wants data after every 30.30 ns but memory can make it available only after 60ns+10ns(memory cycle time+circuit delay)= 70 ns Now, >make CPU wait by adding 1 WAIT STATE(i.e. add 30.30 ns to its making demand of data) after adding 1st WAIT state, CPU will need data after 60.60 ns.. since memory cant make data available still...so >make CPU wait by adding 1 more WAIT STATE(i.e. add 30.30 ns to its making demand of data) after adding 2nd WAIT state , CPU will need data after 90.90ns ...since now memory has already made data available by 70ns ...so no more waiting for CPU and CPU will continue with its work... Thus, we have to add 2 WAIT STATES ........(ANSWER)
4 votes
4 votes
And is D

Wait state is no. of cycles spent in operation of memory access. I.e $\frac{Total memory access time}{time taken by CPU}$

Let us first calculate the total memory access time required to access memory I.e. 60ns + 10 ns.

Now the time taken by CPU is $\frac{1}{33MHz}$

which equals 30.30 ns

Now no.of wait states will be $\frac{70 ns}{30.30 ns}$ = 3(approx)
3 votes
3 votes
https://en.wikipedia.org/wiki/Wait_state

Wait state is no of cycles spent in operation of access

So it should be 33MHz implies 30.30 ns

and total memory access time will be 60+10=70ns

so no of cycles or wait states =70/30.30=2.31=3.(should be integer)
Answer:

Related questions

5 votes
5 votes
2 answers
1
Sourabh Kumar asked Jun 22, 2016
5,760 views
Assume that $16$-bit CPU is trying to access a double word stating at an odd address. How many memory operations are required to access the data?$1$$2$$3$$4$
10 votes
10 votes
6 answers
2
ajit asked Aug 15, 2015
10,320 views
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4 \times 6$ array, where each chip is $8\...
7 votes
7 votes
2 answers
3
ajit asked Aug 15, 2015
6,633 views
Suppose you want to build a memory with $4$ byte words and a capacity of $2^{21}$ bits. What is type of decoder required if the memory is built using $2K \times$ $8$ $\te...
6 votes
6 votes
1 answer
4
ajit asked Sep 8, 2015
5,404 views
The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is ______$1$$2$$8$$16$