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In the circuit shown below, the propagation delay of each NOT gate is 2 nsec, then the time period of generated square wave is –

I think it should be 22ns but it is given 20ns

Suppose at time 0 the output at last FF ( right most FF) is 0

Then at time 12 nsec output will change from 0 to 1

But the first FF get the input at 10nsec and thus the output at last FF will change from 1 to 0 at 22nsec.

So, the output changes 0 -> 1  -> 0 in 22nsec.

Where I am doing wrong.

in Digital Logic by Boss (18.3k points)
edited by | 1.2k views
+1
why isn't the answer 20 nsec? The output will change after every 5 * 2 = 10nsec. The last not gate will just delay the whole wave by 2 nsec, but not affect the time period.
0
Oh yes it is 20nsec.

But why not 22nsec as the final output will be present at the rightmost FF?
+1
ff?? you mean NOT gate??

rightmost NOT gate will delay the output by 2 nsec. So, the wave will be out of phase from the wave without the rightmost gate. But there will be no change in the time period. You will get it better by drawing it's waveform.
0
right most not gate only shift he wave in right direction but cannot change the time period thats why we are taking 20ns time period. which is equal to 2*n*(Delay of each not gate).

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by Boss (15k points)
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what is the reason for this multiplication by 2?
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