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in Digital Logic
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Given, current state = q and next state = Q

a) In S-R f/f, the two inputs S and R denotes Set and Reset respectively. So, a "1" in S and "0" in R is used to set the f/f, similarly, a "0" in S and "1" in R is used to Reset the f/f(i.e. set it to 0). The input S = 1 and R = 1 is not used, since after that the f/f is in an undetermined state.

So, on input S = 1 and R = 0, we have Q = 1 (irrespective of previous state).

b) In J-K f/f, we have J and K instead of S and R. So, we have a similar truth table, except now the invalid input in SR f/f (S = 1 and R = 1), is now a valid input and is used to toggle the state of f/f.

On J = 0 and K = 0, we have Q = q (i.e. no change in f/f state). (see the table)

c) We have J = 1 and K = 1 to toggle the f/f state. (see the table)

d) In negative-edge triggered f/fs, the state of the f/f changes only on the falling edge (or negative edge) of the clock.

In the diagram above, the triangle with a bubble (small circle) in the clock input indicates that it is negative edge triggered. The absence of that bubble will indicate positive edge triggered.

e) same as b part.

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a.   1

b.     q

c     j=1,k=1

d

e   q
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a) If clock=0 then Q=q , other wise its Q=1.

b) Whatever is the clock value , for J=0 and k=0 it will restore its previous value i.e. Q=q.

c) For purposefully reversing the outputs use J=1 and k=1 and also clock=high(1).

e) Irrespective of the clock it will restore its value i.e Q=q.