throughput

Question

The 5 stages of processor fetch, decode, execute, memory and writeback have the following delays 100, 120, 200, 110 and 150 nanoseconds respectively. Assume that when pipelining, each pipeline stage costs 20ns extra for the registers between pipeline stages. If one of the pipeline stages is split into 2 equal halves to increase the throughput, what is the new throughput (in Million Instructions per second)

1.   3.44 MIPS
2.   10 MIPS
3.   5.88 MIPS
4.   6.55 MIPS

Comments

After splitting the pipeline, stage delays will be 100,120,100,100,110,150

the cycle time of pipeline = largest phase delay + buffer delay

                                         = 150 + 20 = 170 ns

CPI should be 1 which is the main aim of pipelining...

"Number of instructions can be executed in 1 second is throughput"

1 instruction ----------------  170 ns

10^9/ 170 Instruction ----------------------- 1 sec

1000 Million/ 170 Instructions -------- 1sec

5.8832 MIPS

---

how to know which stage should be split?

---

@mittal

to increase throughput always split the stage with highest delay

---

Change ur comment to answer @akash.dinkar12

Answer 1

After splitting the pipeline, stage delays will be $100,120,100,100,110,150$

the cycle time of pipeline $=$ largest phase delay + buffer delay

                                         $= 150 + 20 = 170 \ ns$

CPI should be $1$ which is the main aim of pipelining...

"Number of instructions can be executed in 1 second is throughput"

$1 \ instruction ----------  170 ns$

$10^9/ 170\ Instruction -------   1 \sec$

$1000 Million/ 170\ Instructions -------- 1\sec$

$5.8832 MIPS$