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Given main memory size   =    4 GB

   Hence number of bits needed for CPU generated address  =   log2 (4 G)   =   32 bits [ Assuming byte addressable ]

Given cache memory size   =    64 KB 

  Number of cache lines       =    32

  Hence line size                 =    Cache memory size / Number of cache lines

                                         =    216 /  25

                                         =    211 B

Hence number of bits needed for line(block) offset   =  11 bits

Number of sets                   =   Number of lines / Associativity

                                         =   32 / 4    =   8

Number of bits needed for set index      =   log2 (Number of sets)

                                                          =   log2 8     

                                                          =   3

Hence number of tag bits                      =  Total address length - Set offset - Block offset

                                                           =  32  -  3  -  11

                                                           =  18 bits

And extra bits needed                            =  4  [ as mentioned in the question ]

Hence in cache controller number of bits associated for each cache line   =   18 + 4  =  22 bits

Hence total tag overhead in cache controller       =     Number of cache lines * Tag overhead for each line

                                                                       =     32 * 22

                                                                       =     704 bits

The options are wrongly framed in the question..

                                                       

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ASAIK for Tavg(read) = T(read) = HR(read) * Tc + (1-HR) * (Tc+Tm)but while calculating they have neglected Tc in (Tc+Tm)...Please verify ??