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+2 votes

computer uses addressing modes to reduce the number of bits in the addressing field of the instruction

Can someone please explain how this statement is true? PLEASE

Examples will be helpful

asked in CO and Architecture by Boss (16.5k points) | 347 views

1 Answer

+9 votes
Best answer

This statement is true actually..

As far as the instruction length is concerned , instructions are divided into two types :

a) Fixed length instructions

b) Variable length instructions

Most of the architectures now use fixed length instructions . So in such instructions , the instruction length as a whole is fixed but its field's length can be altered in turn hence to achieve the same..

Say I have instruction of length 20 in which there is an opcode field of 6 bits and two address fields(one say for source and one for destination) each of 7 bits..

Now say if we need one address instruction while keeping instruction length fixed i.e. 20 bits..So what we do is we use a technique known as expanded opcode technique..So one address field is now appended as a part of opcode..

Hence now opcode bits =  13 bits and addressing bits  =  7 bits. as opposed to 6 bits of opcode and 14 bits of addressing in earlier case..

If we see w.r.t previous type of instruction i.e. 2 address based one , it is for instructions like register to register transfer..But say for stack based instruction in which entire bits are meant for opcode only and no addressing field , the addressing mode is implied addressing mode.

So by variation of addressing modes , we are getting different types of instructions , specifically different number of bits for addressing in each case..Hence the statement should be true.

answered by Veteran (101k points)
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Thanks :)

Habib Bhai has already well answered...

I want to add some points.

Depending on the residence of a variable, the number of bits in the addressing field of instruction will vary.

In the sense, our CPU is executing an instruction and that instruction says that the operand is available in memory or in registers or in the instruction itself. Depending on the availability of operand decrease in the number of bits.

Let us take an example we have a Main memory of 1M*32, There are 220 locations in main memory and size of each location is 32 bits. If we want to say that suppose the variable that is needed in some program in the present in somewhere in memory, in an address to address this variable we need 20 bits, So, in this case, our instruction size will be very big because we need at least 20 bits to represent the location of variable.

In the same way, suppose there are 32 registers in our program, suppose that variable resides in one of the registers, now we need only 5 bits. we have dropped down from 20 to 5 bits.

So the number of bits have reduced in the addressing field of instruction...


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