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Cache size 32 KB

Block size = 32 Bytes

Address size = 28 bit.

Associativity of Cache = 16

Determine what is the hardware requirement to design the 16-way set associative cache.

Hardware requirement -> Mux, Comparator, Demux, Decoder, Encoder etc.

My answer:-  Our requirement are as follow:-

1) 64 Comparator each of size 4 bit.

2) 1 Decoder Dimension -> 6 X 64

3) 1 Mux Dimension -> 32 X 1 where number of select lines are 5.

4) 64 And gates

5) 1 OR gate input line = 64

Someone, please verify these attributes??
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comparators-> 16, size=17bits

size of one MUX-> 64$\times$1 //since there are total 64 sets.
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@joshi_nitish you are selecting one set out of 64 sets. if yes then how will you extract a particular word from a particular block?

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there will be 16(no of lines in one set) parallel MUX doing same thing..
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3 Answers

5 votes

Number of cache block = $\frac{2^{15}}{2^5}$ = $2^{10}$

Number of sets = $\frac{2^{10}}{2^4}$ = 64

Address Size = 28 bits

|17|6|5| = |tag bits|set index bits|Block offset|

number of comparators required = 16 ( 16 blocks in 1 set)

Each comparator size  = number of tag bits = 17 bits comparator

MUX required of size Kx1 : 16x1 MUX

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I think Mux should be 32 X 1, as we have 5 bits for word offset.

and Decoder will take 6 binary bits and select 1 set out of 64 sets.
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where did you study this?
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I am reading this at the first time, just asking.
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@Manu

MUX size = # of sets$\times$1..

so it should be 64$\times$1...isn't i?
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@nitish MUX size is Kx1, where cache is K associative, because there are k blocks in a set, when tag bits of a block matches with the cpu generated tag bits, required word from that block will be transfered to CPU, so we need kx1 MUX to output one tag out of k stored k tags in 1 set.
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ok...i was using different hardware implementation(not standard), but it was very complicated..
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which part of address will be selected as select lines in 16 X 1  MUX?
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@manu is the number of multiplexers required 17*64 (17 multiplexers per set) ? Please add that information to your answer.
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i think @nitish is right @manu

because we 1st take the set no. bit apply them as input to multiplexer to locate the set no. and then use comparator to compare the tag bits in above example 16 comparator (16 lines per set are used) and then use or gate

therefore the no. of multiplexer would be 64 to 1 mux

correct me if i am wrong
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i didnt understand this explanation
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no. of comparator in n-way set associative = n

size of each comparator = no. of bits in Tag field

so, no. of comparator = 16

size of each comparator = 17
3 votes
i think @nitish is right @manu

because we 1st take the set no. bit apply them as input to multiplexer to locate the set no. and then use comparator to compare the tag bits in above example 16 comparator (since 16 lines per set are used) and then use or gate

therefore the no. of multiplexer would be 64 to 1 mux
in above example even you have used decoder of size 6 to 64
correct me if i am wrong
1
correct mux  size is 64 * 1
0 votes
Tag bit= 17, set bit= 6, offset bit= 5

Firstly 1 multiplexer or set index decoder(size 64 x 1) will be used to reach the required set, then all tag bits of 16 lines in that set will be matched with the help of 16 comparators of size 17(tag bits). Don't bother yourself on how to fetch all tag bits from 16 lines (we could use multiplexer same as we fetch from Associative mapping) because that is advance topic and not required for GATE. Then lastly we required an OR gate or a multiplexer(mux. can work as an "OR" gate) to check whether there is a hit or miss.

Note- A comparator compares 1 bit at a time that's why T.comparator= K * comparator latency

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