CO:- Memory Access time

Question

Answer 1

According to the question , when a cache miss occurs , following course of action will be taken..Let us write the delay for each action :

a) Detecting cache miss time  :  It is given the same as cache hit time .Hence time taken here   =    5 ns

b) Transferring first word of the main memory block to cache line :   Here given time             =    90 ns

c) Transferring remaining words from main memory to cache line : 

Here we need to find the number of words that can be stored in one cache line.

Hence number of words           =     Line size / Word size

                                             =     64 B / 2 B

                                             =     32

Hence number of words remained to be sent  =   32 - 1  = 31

Latency to transfer each of these words given    =   10 ns

Hence total time taken to transfer these words   =    31 * 10

                                                                      =    310 ns

d) Re executing memory fetch instruction which will lead to cache hit : For that again we need time equivalent to cache hit latency..Hence time taken here                         =    5 ns

Hence total time taken                                     =    5 + 90 + 310 + 5

                                                                      =    410 ns

Hence total time incurred should be 410 ns in case of cache miss as per the events mentioned in the question..

Comments

I think by the hierarchical access ,we know whenever there is a miss,then after bringing data from main memory to cache CPU will re execute. But the defined formula for hierarchal dont consider that time.

Tavs =  H*Tc +(1-H)(Tm+Tc) // now i have seen some questions,where we say:-

example question:- Cache access=5ns,Memory Access=60ns.Disk access=100ns. In case of miss copy data from memory to cache in 60ns.In case of memory miss,copy from disk to memory in 100ns and disk to cache in 60ns and then access.

So here, if we assume hierarchal and then at each level we add all the time we already spent in higher level and the current level access time.We ignore the time to take data back to cache and re execute.Or it may be included in the 60ns or 100 ns.Thats why i think 405 is correct.

May be i will look some standard question and update

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@Habib @rahul correct answer is 405ns only, for details see my answer!

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 rahul sharma 5

here this is mentioned in the question that ..."we will ignore the time to write line into cache once it has been fetched from MM.."   therefor ...(5+90+31*10)

Answer 2

Time needed when Cache Miss= 90+31*10 + 5 = 405ns  is the correct answer.

Cache line size  64Bytes, 1 word size=2B, total number of words to be fetched from memory to cache = 64B/2B = 32

First word needs 90ns and subsequent 31 words need 10 ns each. 

Why don't we need to add the 5ns to check if it's cache hit or miss? because address is simultaneously sent to both the cache and th main m/m as shown:

Comments

I think it depends whether it is simultaneous organization or hierarchal organization.In hierarchal CPU access from level 1 only If not there then it will bring from main memory. And we assume that this time is included in memory access time.

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Actually these type of questions should be framed very precisely as the overall concept is broad here and is situation dependent ..

I can show an example which contradict ur answer @Manu Thakur ..I would suggest u to go through the same carefully and compare it with that of the constraint given in the question..:) 

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@Habib yes, you're right! such questions should be framed very precisely. In the screenshot mentioned by you they explicitly mentioned that " the miss penalty also includes a delay of t".