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Consider a 6 staged pipelined processor , where all stages are perfectly balanced. While executing a branch instruction CPU computes the target address after completing the operation in 5th stage only.One clock cycle time is required for executing one non branch instruction.Let the system frequency is 1GHz and it takes 1.6sec time for 109 instructions, then number of branch instructions in the above program is ?

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Here cycle time  =   1 / (1 GHz)    =   1 ns

Here CPInon branch  =   1 which is default assumption also (CPI of an ideal pipeline is 1)..

Time taken by 109 instructions  =   1.6 s

Hence time taken by 1 instruction    =   1.6 ns

Hence number of cycles taken by 1 instruction  =   Time taken by 1 instruction / Cycle time   =   1.6

Hence CPIeffective    =     1.6

But we know CPIeffective   =   1 + Number of Stalls / instruction   

                                      =   1 + (fraction of branch instruction * branch penalty)..

                                      =   1 +  x * branch penalty

Now

Branch penalty  =  Stage at which target address is found for the branch location - 1

Now the stage is given as 5th stage..Hence branch penalty  =  4

Hence  

             CPIeffective    =     1 + x * 4

==>      1.6                =     1 + 4x

==>      4x                 =     0.6

==>      x                   =     0.15   =   15 %

Hence number of branch instructions     =   (15/100) * 109

                                                          =    15  *  107  branch instructions

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Total no of stages = 6

cycle time =1ns

target address is available at 5th stage , so branch penalty will be 4.

total no of instructions are 10^9 which takes 1.6 sec to execute

Let x is no of branch instructions.

total branch penalty = 10^9 * x * 4 cycles.

non branch instructions are taking one cycle

total execution time = [1 + #f stalls ] * cycle time

1.6 sec = [ 1 + 10^9 * x * 4 ]* 10^-9

=> x=0.15

=> x=15%

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1 votes
Total time=no. of branch instructions*time taken by each branch instruction+ no. of non branch instruction* time taken by each instruction.

let suppose there are K no. of branch instruction. Given that it will target address at the end of 5 stage. So there will be BRANCH PENALTY of 4 because of 4 stall. so CPI=1+branch penalty=4+1=5.

clock frequency = 1ghz  =>>>>> clock time =1ns

total time= ( K*5+ ( $10^{^{9}}$ -K )*1 ) *1ns.

1.6=(K*5+( $10^{^{9}}$ -K )*1 ) *1ns

1.6*$10^{^{9}}$ =  (K*5+( $10^{^{9}}$ -K )*1 )

1.6*$10^{^{9}}$ = 4K+ $10^{^{9}}$

0.6 * $10^{^{9}}$  = 4K

K= 0.15 *$10^{^{9}}$.

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