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in CO and Architecture by Boss (25.2k points)
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6450 Bytes ??
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since genreally one micro insrctn take 1 clock cycle to complete, and each isrctn take 10 clocks and there total 258 insrctns, this means,

# of micro instrctns(control words)= 258*10 = 2580

in vertical μ progrmming, bits for control signal = log(#of conrol signals)= log129 = 8 //taking ceil

also, in μ progrmmng, each addr correspond to one control word, therefore # of addr bits = log2580= 12

and no mux selector lines are mentioned in qsn, so take it 0...control word will look like.

8(cotrol signal) 12(addr)

size of one conrol word = 20 bits + 4 bits(padding to make it next multiple of 8, because memory is by default byte aligned)

total size of control memory = 24*2580 bits = 7740 bytes. 

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@joshi_nitish What if the memory is given as word addressable and 1 word=20 bits. Is this scenario possible? If yes then how would we access the locations in that case?
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@nitish, size of control memory = no. of instructions * control word size

what is the need to multiply no. of instructions by 10 clock cycles ? also i think no padding is required
+1

@bhavna,

size of control memory(μ instructn control memory) = no. of micro instrctns * control word size

// now, 1 instrctn take 10 clocks means one normal instruction = 10 μ instrctns(because in genral one μ instrctn take 1 cycle)...so total μ instrutns = 258*10 = 2580...

instrctn can never be fractional multiple of byte, because byte is atomic unit, you can never fetch instructions, data etc in fractional multiple of bytes..

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@Upasna singh, if memory would be word addressable then also, one word = some integral multiple of bytes...

one word = 20 bits = 2.5 bytes  //this is not possible..
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I agree but isn't memory stored in terms of control word ? and here control word is 20 bits
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but that control word will be saved as 24 bits....
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@nitish it's not true that the size of microinstruction format be a divisible of 8. see the following screenshot:

In fact, there is no field mentioned for padding.

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http://faculty.washington.edu/lcrum/TCSS372AF09/15_Control.ppt

Control word need not to be multiple of 8
+1
@Manu

thanks, now i read it and what i found is that μ instructions are stored in ROM, and in ROM 1 word need not be integral multiple of bytes.
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joshi_nitish

If the address require 12 bits,then we should have 2^12 addressable locations?

So we should do 2580*20 bits or 2^12 * 20 bits?

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12 bits, we have used because it is minimum bits to show 2580 control words...

2580*20 is correct answer.

1 Answer

+3 votes

TotaL MICROINSTRUCTIONS=2580
SIZE OF ADDRESS FIELD=CEIL(LOG(2580))=12
CONTROL SIGNALS=129
TOTAL CONTROL BITS IN ENCODED CONTROL FIELD=CEIL(LOG(129))=8
SIZE OF CONTROL WORD=20 BIT
TOTAL SIZE OF CONTROL MEMORY=20*2580 BITS= 6450 BYTE

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