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Question

1)A pulse train with a frequency of 1MHz is counted using a modulo 1024 ripple - counter built with JK flip flops. For proper operation of the counter  the maximum permissble propagation delay per flip - flop stage is .

2)The 2's complement representation of (-539)₁₀ in hexa decimal is 

3)To Realize a half adder circuit , _____ no. of two input NAND gates are required .

4)In the circuit shown in the figure, if C = 0, the Expression for ' Y' is 

Answer 1

  A_i_$_h Plz refer following links:

1: https://gateoverflow.in/120428/isro-2006-ece-ripple-counter

https://gateoverflow.in/102580/gate1993-ece

2: https://gateoverflow.in/728/gate2001-2-10

3: http://www.geeksforgeeks.org/half-adder-half-subtractor-using-nand-nor-gates/

4: https://www.aspirebuzz.com/content/circuit-shown-figure-if-c-0-t