Cache design and Memory Access

Question

Comments

@neelesh bhakt The form which you have mentioned in your equation is of hierarchal access not simultaneous. And moreover, in the question, it is nowhere mentioned that "on the miss in Li level cache the block of data is transferred from L(i+1) level to Li ", so why we are considering that equation?

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By sequential access i meant hierarchical access only..
When there will be a miss in L1 we have to add the time of accessing L1 since access is sequential(L2 after accessing L1) not simultaneous to both L1 and L2.

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How you write x+y+0.1*100 is miss penaty of L1?

Answer 1

Miss penalty means the time taken to transfer a block from main memory to cache if it is not found in cache which is L1 in this case.

Miss penalty in L1=present in L2 + not present in L2

                             =0.9(x+y)+0.1(x+y+100)=x+y+10=25(given)

therefore,x+y=15.