0 votes 0 votes For a N-stage ripple carry counter which uses flipflops of propagation delay = P ns and clock period of C ns. Give the expression of the frequency of input signal? Digital Logic digital-logic digital-counter + – Tuhin Dutta asked Nov 17, 2017 Tuhin Dutta 991 views answer comment Share Follow See all 5 Comments See all 5 5 Comments reply joshi_nitish commented Nov 17, 2017 reply Follow Share in ripple counter, to work properly, Tclock is in prior adjusted as below given eqn Tclock >= N*Tflip_flop therefore entire input frequency will be frequency of input clock therefore input frequency = $\frac{1}{C}$Ghz 0 votes 0 votes Tuhin Dutta commented Nov 17, 2017 reply Follow Share So the following is incorrect. right? $X = T_{clock} + N*T_{flipflop}$ $Input freq \leq \frac{1}{X} GHz$ In one of the madeeasy solutions this was given so I wanted to confirm. 0 votes 0 votes joshi_nitish commented Nov 17, 2017 reply Follow Share yes, it is incorrect. 1 votes 1 votes Shubhanshu commented Nov 17, 2017 reply Follow Share Check this diagram. 0 votes 0 votes Tuhin Dutta commented Nov 17, 2017 reply Follow Share So according to your diagram for this eqn. to satisfy Tclock >= N*Tflip_flop N must be 1. Am I understanding it correctly? I'm weak in these timing diagrams. Thanks 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes Propagation delay for a Ripple counter is given by formula = Tpropagation−delay=n∗Tflipflops+Tcombinational. Where Tpropagation−delay= 1/frequency(f) where Strobe Signal's delay has to be treated as an additional Combinational crkt delay... Namit Dhupar answered Nov 22, 2017 Namit Dhupar comment Share Follow See all 0 reply Please log in or register to add a comment.