Given question is: Consider the following program segment used to execute on a risc pipleline where all the stages are taking 1 cycle to complete the operation except MA stage (4th stage ). MA stage takes two cycle to complete opeartion. How many cycles are are required to complete the program
i1: Load r0, 3(r1)
i2: mul ,r3 r0,r1
i3:Load r4, 4(r2)
My doubt is in the pipelining diagram why we are not decoding i3 when stalls are there for i2 in clock cycle 4 and 5
Oops, Sorry I was wrong! you can use EX for Load and Store but not in case of MOVE operation..
And yes, coming to your doubt this is done in order to prevent any kind of Data Hazards.
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There is one more problem. Ppl who have...