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Given question is: Consider the following program segment used to execute on a risc pipleline where all the stages are taking 1 cycle to complete the operation except  MA stage (4th stage ). MA stage takes two cycle to complete opeartion. How many cycles are are required to complete the program

i1: Load r0, 3(r1)

i2: mul ,r3 r0,r1

i3:Load r4, 4(r2)

i4:Sub r5,r4,r6

My doubt is in the pipelining diagram why we are not decoding i3 when stalls are there for i2 in clock cycle  4 and 5 

asked in CO & Architecture by Active (1.1k points)
edited by | 58 views
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Is there any mention in the question that operand forwarding is to be used? And always keep in mind, you cannot Use EX instruction for LOAD AND STORE OPERATION!
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yes operand forwarding is to be used
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Ok but try to not use ex instruction for load and store! As no ALU is used for this! And recheck the answer, I am sure you'll get that right this time
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Still having some confusion. Can you just explain it a bit ??

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Oops, Sorry I was wrong! you can use EX for Load and Store but not in case of MOVE operation..
And yes, coming to your doubt this is done in order to prevent any kind of Data Hazards.

Go to page number-10 of this link
https://cseweb.ucsd.edu/classes/wi14/cse141/pdf/05/04_Elsevier_pipeline.ppt.pdf 

answered by Active (1.5k points)


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