Given question is: Consider the following program segment used to execute on a risc pipleline where all the stages are taking 1 cycle to complete the operation except MA stage (4th stage ). MA stage takes two cycle to complete opeartion. How many cycles are are required to complete the program
i1: Load r0, 3(r1)
i2: mul ,r3 r0,r1
i3:Load r4, 4(r2)
i4:Sub r5,r4,r6
My doubt is in the pipelining diagram why we are not decoding i3 when stalls are there for i2 in clock cycle 4 and 5