I think $, D, JK or SR-Flip Flop$ any one of them could be used.
What is your opinion Praveen Saini ji ?
@Surajit ji, Your opinion looks elegant and correct.
@Surajit brother can you please show via diagram ,your approach by using only two FFS
Sequence given is as
From the given sequence of states we can design the state table and Suppose we are using T-FF for sequential circuit of counter.
From the above table , we will find the equation of $T_A$, $T_B$ and $T_C$
Tuhin Dutta HOW?
If we use ripple or jhonson counter we can make it, right? Since for k FF we can have 2k or 2k states respectively.
Hi @Praveen Saini ji,
Thanks for your valuable effort. But to make circuit more error tolerant instead of using DO NOT CARE. We should move to some valid state from Invalid state.
@Chhotu @Praveen Saini
Can we implement any sequence of 4 distinct states
With 2 FFs
like 0,7,1,9,0,7,1,9.. ?
@jatin khachane 1
https://gateoverflow.in/2117/gate2011-15 check this question.
We can have log n FF for n states. We just have to design the combinational circuit which will provide the appropriate input during next clock cycle to count those many states.
Generally synchronous counter are designed by using D- flip flop and asynchronous counter are designed by using T- flip flop. So here counter designed by using D flip-flop
When will be the final official key...