23 votes 23 votes Design a synchronous counter to go through the following states:$$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $$ Digital Logic gate1998 digital-logic normal descriptive synchronous-asynchronous-circuits + – Kathleen asked Sep 26, 2014 Kathleen 5.1k views answer comment Share Follow See all 7 Comments See all 7 7 Comments reply Show 4 previous comments Abir Mazumder commented Sep 25, 2020 reply Follow Share We need 2 FF counter , 3 FF system has redundancy . PARDON MY DRAWING :p 1 votes 1 votes jatinmittal199510 commented Apr 12, 2021 reply Follow Share @Abir Mazumder, correct solution. Moreover, the function that we will use to map to the desired state number will be $2Q_1 + Q_0 + 1$ 0 votes 0 votes svas7246 commented Aug 15, 2022 reply Follow Share This counter has various way to derive it for the states it depends on the flipflop you choose to use and when you actually draw the k maps which dont care’s do you use all these will come in to play 0 votes 0 votes Please log in or register to add a comment.
Best answer 28 votes 28 votes Sequence given is as $ 1,4,2,3,1\ldots$ From the given sequence of states we can design the state table and Suppose we are using T-FF for sequential circuit of counter.$$\small \begin{array}{|ccc|ccc|ccc|}\hline \rlap{\textbf{Present State}}& & & \rlap{\textbf{Next State}} & & & \rlap{\textbf{FF Inputs}} & & & \\\hline \;\; A\;\; &\;\; B\;\; &\;\; C \;\; & A^{+} & B^{+} & C^{+} & T_{A} & T_{B} & T_{C} \\\hline 0 & 0 & 0 & x& x & x & x & x & x \\\hline 0 & 0 & 1 & 1&0 &0 &1 &0 & 1 \\\hline 0 & 1 & 0 & 0&1 &1 &0 &0 & 1 \\\hline 0 & 1 & 1 & 0&0 &1 &0 &1 &0 \\\hline 1 & 0 & 0 & 0&1&0 &1 &1 & 0 \\\hline 1 & 0 & 1 & x& x & x & x & x & x \\\hline 1 & 1 & 0 & x& x & x & x & x & x \\\hline 1 & 1 & 1 & x& x & x & x & x & x \\\hline \end{array}$$From the above table, we will find the equation of $T_A$, $T_B$ and $T_C$ Praveen Saini answered Jan 13, 2016 • edited Jul 16, 2019 by Lakshman Bhaiya Praveen Saini comment Share Follow See all 22 Comments See all 22 22 Comments reply Manu Thakur commented Jun 17, 2017 reply Follow Share Is it necessary to cover all the possibilities? I mean we can only make the k-map for 1->4->2->3 and then i can find the Input expression for all three flipflops. 1 votes 1 votes Praveen Saini commented Jun 28, 2017 reply Follow Share Need to fill at minterm loc in kmap while finding expression. 0 votes 0 votes Tuhin Dutta commented Sep 9, 2017 reply Follow Share since there are 4 distinct states ( 1,4,2,3 ) can we use only two flipflops? 5 votes 5 votes set2018 commented Sep 14, 2017 reply Follow Share Tuhin Dutta HOW? 0 votes 0 votes Tuhin Dutta commented Sep 14, 2017 reply Follow Share If we use ripple or jhonson counter we can make it, right? Since for k FF we can have 2k or 2k states respectively. 0 votes 0 votes Praveen Saini commented Sep 15, 2017 reply Follow Share @Tuhin, you are right. 0 votes 0 votes Tuhin Dutta commented Sep 15, 2017 reply Follow Share Might we need some extra logic gate to represent state 4? 0 votes 0 votes Praveen Saini commented Sep 16, 2017 reply Follow Share yes.. 0 votes 0 votes Tuhin Dutta commented Sep 16, 2017 reply Follow Share Thanks for clarifying it, sir. 0 votes 0 votes rajoramanoj commented Dec 6, 2017 reply Follow Share here sequence is given then why are you not following the given sequence only like (1 4 2 3 1 4 2.......). means why are you covering all like(1 2 3 4 5 6 7 ). 0 votes 0 votes sid1221 commented Dec 10, 2017 reply Follow Share ripple is asyhnchronous it s asking about synchronus 1 votes 1 votes Praveen Saini commented Dec 13, 2017 reply Follow Share @rajoramanoj, from state sequence we get state 4 where we need 3 bits to represent,100, with 3 bits we have 8 combinations 0 to 7, those state are not in sequence are unused states, for those next state is shown as dont cares. 3 votes 3 votes Chhotu commented Dec 29, 2017 reply Follow Share Hi @Praveen Saini ji, Thanks for your valuable effort. But to make circuit more error tolerant instead of using DO NOT CARE. We should move to some valid state from Invalid state. 0 votes 0 votes Gate Fever commented Sep 4, 2018 reply Follow Share why Tb is not A+BC? why B XNOR C?? acc to me Tb should be A+BC. 5 votes 5 votes jatin khachane 1 commented Nov 9, 2018 reply Follow Share @Chhotu @Praveen Saini Can we implement any sequence of 4 distinct states With 2 FFs like 0,7,1,9,0,7,1,9.. ? 0 votes 0 votes tusharp commented Dec 13, 2018 reply Follow Share @jatin khachane 1 https://gateoverflow.in/2117/gate2011-15 check this question. We can have log n FF for n states. We just have to design the combinational circuit which will provide the appropriate input during next clock cycle to count those many states. 0 votes 0 votes jatin khachane 1 commented Dec 13, 2018 reply Follow Share Yes thats right ..but here to represnt 7 ..we need 3 bits ..1 FF output ==> 1 bit eg 2 FFs ..FF1 ==> Q0,...FF2 ==> Q1 0 votes 0 votes tusharp commented Dec 14, 2018 reply Follow Share yes correct. depends on input. 😊 0 votes 0 votes Abir Mazumder commented Sep 25, 2020 reply Follow Share Why do we need 3 FF ? there are 4 distinct states and and we can very well make this counter with 2 FF . 00 for state 1 , 01 for state 2 , 10 for state 3 and 11 for state 4 0 votes 0 votes jatinmittal199510 commented Apr 12, 2021 reply Follow Share Can be done using $2$ FF's. Function that we will use to map to the desired state number will be $2Q_1 + Q_0 + 1$ 0 votes 0 votes JAINchiNMay commented Jun 17, 2022 reply Follow Share In the k-map for Tb why you have not considered 4sized subcube i.e. A+BC 2 votes 2 votes Abhrajyoti00 commented Jan 6, 2023 reply Follow Share @JAINchiNMay Yes, it should be A+BC. 0 votes 0 votes Please log in or register to add a comment.
2 votes 2 votes Using D-FlipFlops An Bn Cn An+1 Bn+1 Cn+1 0 0 0 X X X 0 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 X X X 1 1 0 X X X 1 1 1 X X X After minimizing An+1, Bn+1, Cn+1 using K-Map An+1 = Bn’C Bn+1 = Cn’ Cn+1 = B mayankso answered Dec 8, 2020 mayankso comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes Generally synchronous counter are designed by using D- flip flop and asynchronous counter are designed by using T- flip flop. So here counter designed by using D flip-flop ravi rajak 3 answered Oct 14, 2017 ravi rajak 3 comment Share Follow See 1 comment See all 1 1 comment reply rajinder singh commented Aug 24, 2018 reply Follow Share D1=not(Q0) only 2 votes 2 votes Please log in or register to add a comment.