If you see at clk 4 the Instruction queue length is 1. Now think when can it be 1? Only when at clk4 the already present instruction of queue i.e. I3 is now at dispatched/decode stage and in same clk4 I4 is being fetched into queue, though diagram it is shown at clk 6(which is correct according to convention) it could even be placed at clk 5, thus at clk 6 only I5 is being dispatched and decode.
I hope this explanation goes with Carl, but this is what logically possible otherwise no two instruction can perform in the same stage in the same cycle.
Let me know if I am going wrong somewhere. Peace.