Address Translation

Question

Which one is TRUE? Give explaination

1)The main reason to have multilevel page to speed up address translation

2)The main reason to have hardware TLB to speed up address translation

Comments

suppose there is no  paging, CPU will generate direct physical address, no address translation is required.

if single level paging and TLB is used,TLB is associative memory, search happens in parallel, very negligible time to search in TLB and direct physical address (frame number) is found . if single level paging no TLB, first you fetch page table from memory look for the page table entry and then get frame number.

if two level paging first you fetch outer page table then inner page table then you get frame number or actual physical address. it means every time you increase the  levelof paging, it will increase one more level to get the physical address. more number of levels of paging will result in more indirection to address translation

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yes, true, but what about 1)??

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We want to keep part of process that we want to run and its page table in main memory. That means put complete page table in one frame. But sometimes page table size is so big that it cannot be placed in one frame. so we again divide this table into many pages.

Lets see one example: virtual address 72bits, pages size 1GB, page table entry 4B so one 1 frame size = 1GB

and page table size = $2^{72}$/$2^{30}$= $2^{42}$ * 4 = $2^{44}$ which is more than our frame size so we need help of one more page table and so on.