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Definition of Ideal Pipeline

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In computer when we measure the performance of CPU in CPI that is clock per instructions..means how may clock cycles are needed to execute 1(single) instruction...

SO to get max output we have implemented pipelining...in which under idle condition CPI=1...means we are able to execute one instruction at one clock of CPU....for that we divide the COMPETE WORKING OF PC into modules like 

FETCH,DECODE,EXECUTE,WRITE-BACK...and we perform them in pipelining.....

While in actual implementation ..due to DATA dependence or branch instruction we failed to get CPI=1..and CPI increases to 2 or 2.5 or more as per dependency...
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i found out this formula :

Pipeline CPI=Ideal Pipeline CPI +Structural Stalls + RAW Stalls  +WAR  Stalls+ WAW Stalls +Control Stalls

so ideal pipeline is a pipeline with no stalls in it.
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