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24 votes
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Design a $3$-bit counter using D-flip flops such that not more than one flip-flop changes state between any two consecutive states.
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4 Answers

Best answer
33 votes
33 votes

State diagram will be as  (remember concept of $\textsf{GRAY}$ code) 

State table and $3$-bit synchronous counter with D FFs, will be as 

$\begin{array}{c|c|c}
\text{Present State}&\text{Next State}&\text{FF Inputs}\\\hline
ABC&\bar A \bar B \bar C & D_AD_BD_C\\\hline
001&011&011\\000&001&001\\010&110&110\\011&010&010\\100&000&000\\101&100&100\\110&111&111\\
\end{array}$

 

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5 votes
5 votes
  Present  state       Next state  
Q2 Q1 Q0 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 1
0 1 1 0 1 0 0 1 0
0 1 0 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 1 0 1 1 0 1
1 0 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0

D2=Q1Q0'+Q2Q0

D1=Q2'Q1+Q1Q0'

D0=Q2'Q1'+Q2Q1

3 votes
3 votes

Consider $Q_{A},Q_{B},Q_{C}$ as the $3$ bits, $Q_{A}$ being MSB. The trend taken is that of the $3$-bit gray code. Solve for $D_{a}, D_{b}, D_{c}$  each as a function of $Q_{A},Q_{B},Q_{C}.$ $$\begin{array}{lll|ll}\hline  Q_{A} & Q_{B} & Q_{C} & Q_{A_{n}} = D_{A} & Q_{B_{n}}= D_{B} & Q_{C_{n}}= D_{C}   \\\hline  0&0&0 & 0& 0& 1 \\\hline 0& 0& 1 & 0& 1& 1  \\\hline 0& 1& 1 & 0& 1& 0 \\\hline 0& 1& 0 & 1& 1& 0 \\\hline 1& 1& 0 & 1& 1& 1 \\\hline 1& 1& 1 & 1& 0& 1 \\\hline 1& 0& 1 & 1& 0& 0  \\\hline 1& 0& 0 & 0& 0& 0 \\\hline \end{array}$$

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