Consider a CPU that executes at a clock rate of 200 MHz (5 ns per cycle) with a single level of cache. CPIexecution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic / logical, 30% load / store, 20% control instruction. Assume the cache miss rate is 15% and a miss penalty of 5 cycles. The number of times cpu with ideal memory is faster when no miss-occurs _______.
